A digital signal is formed by modulating a periodic waveform having a fixed clock frequency. FIG. 1 is a diagram illustrating a digital signal 102 and its underlying clock signal 104. For this example, the digital signal 102 is encoded with a data value of logic “1” or logic “0” forming a data sequence 112, and the clock signal 104 forms a clock sequence 114 that alternates between 1 and 0. A transition from 0 to 1 or from 1 to 0 is a signal edge. A transition from 0 to 1 is a rising signal edge, and a transition from 1 to 0 is a falling signal edge. The digital signal 102 represents any arbitrary digital signal having a period 106. The frequency of the underlying clock signal 104 corresponds to the number of periods 106 that occur per second.
In order to analyze the digital signal 102 or receive its data, the frequency of the underlying clock signal 104 must be determined. This is known as clock recovery. In order to receive the data encoded in the digital signal 102, a replica of the clock signal 104 must be generated to demodulate the digital signal 102. This is known as data recovery. A combined process of clock and data recovery where the frequency of the clock signal 104 is determined and used to generate a replica of clock signal 104 is known as clock data recovery.
Clock data recovery is currently implemented in phased-locked loop (PLL) based systems by using the digital signal 102 to phase lock a variable frequency oscillator that generates the replica of clock signal 104. PLL based systems must over-sample the digital signal 102 in order to phase lock to it. For example, in today's products, the digital signal 102 data rate may be 480 Mbps and a PLL will over-sample by 4 times, which calls for a PLL clock rate of about 1920 Mbps. This higher clock rate causes added expend because of higher data rate demands for the PLL system and PLL clock. The higher clock rate may not even be possible to implement, in the PLL based systems, due to its high data rate.
Another way to generate a replica of clock signal 104 is to use a direct digital synthesizer. A direct digital synthesizer is an electronic device for digitally creating arbitrary waveforms and frequencies from a frequency oscillator. A direct digital synthesizer is given a frequency value or a data set that specifies the frequency value, and generates a clock signal at that frequency. PLL based clock data recovery systems are not designed for and are not readily compatible with a direct digital synthesizer.